In this role you will be responsible for the verification of digital/mixed signal ASICs and providing technical insight and proposals related to building complex verification environments. You will capitalize on your experience developing and utilizing top and block level verification environments.
You will participate in all phases of ASIC design & verification with a strong emphsis on verification environments building. Key activities include interpreting high-level design specifications,RTL, behavioral modeling of complexanalog and digital functions and mixed-signal simulation of analog/digital circuits and partnering with system and digital design engineers to ensure the appropriate verification coverage is ensured.
- MASc in Electrical Engineering or equivalent degree
- 4 yrs + of relevent experience in Digital Verification
- Must have : experience in 2 or more of the following: Digital Verification, Mixed Signal Verification, Contrained Random verification techniques
- Must have: recent hands on experience with Synopsys tools and environment, NCVerilog, VCS
- Preferable: VMM, OVM