The Canada R&D Centre, based in Ottawa, is leading research and development of Telecom Network Infrastructure, in 4G/LTE-A, optical, network processing, and switching/router technology as we continued to promote all-IP transformation for our customers.
Position Overview
In this role, you will be responsible for the design of digital / mixed signal ASICs and providing technical insight and proposals related to system architecture. You will capitalize on your experience developing system/block level micro-architecture of DSP.
Responsibilities
You will participate in all phases of ASIC design, verification, physical design and validation. Key activities include interpreting high-level design architecture and creating detailed design specifications, generating RTL, block/top level simulations and timing constraints, behavioural modeling of complex analog functions and mixed-signal simulation of analog/digital circuits, and partnering with layout engineers to ensure the physically correct implementation.
Qualifications
Key qualifications you hold include
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Experience in all steps of the design process
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Writing implementation specifications
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Verilog RTL skills for implementation and verification
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Synthesis (Physical aware synthesis a plus)
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Physical design knowledge a plus
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Expertise with digital design tools for synthesis, place and route, timing closure, equivalency checking, DFT insertion from Synopsys, Cadence or Magma
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Prior design experience using advanced technologies 65nm and below
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A track record with multiple designs in production
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Minimum of 5 years of experience in designing large and high speed ASICs
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A University degree in either Electrical Engineering or Computer Science with a specialization in design
