The Canada R&D Centre, based in Ottawa, is leading research and development of Telecom Network Infrastructure, in 4G/LTE-A, optical, network processing, and switching/router technology as we continued to promote all-IP transformation for our customers.
In this role, you will be responsible for the design of digital / mixed signal ASICs and providing technical insight and proposals related to system architecture. You will capitalize on your experience developing system/block level micro-architecture of DSP.
You will participate in all phases of ASIC design, verification, physical design and validation. Key activities include interpreting high-level design architecture and creating detailed design specifications, generating RTL, block/top level simulations and timing constraints, behavioural modeling of complex analog functions and mixed-signal simulation of analog/digital circuits, and partnering with layout engineers to ensure the physically correct implementation.
Key qualifications you hold include
- MASc in Electrical Engineering or Equivalent degree
- 4 yrs + of relevant experience in Digital Design
- Experience in deep submicron CMOS(65nm or below)
- Must have : experience in 3 or more of the following: Digital specification, RTL, Synthesis, STA, DFT
- Must have: recent hands on experience with Synopsys tools and environment, NCVerilog, VCS
- Preferable: Matlab+Simulink, experience in DSP design