As a key member of our Digital Design group, you will be working in a team environment contributing to design, development and verification of advanced digital subsystems within mixed signal ICs for Semtech’s Signal Integrity Products Division. You will provide guidance to other engineers in the development of our next generation products. As a member of the design group and project team, you will provide high quality design and be accountable for helping the team meet its project milestones and objectives.
As an expert in the field of digital IC design and/or verification, you will be expected to be current in the state of the art design/verification methods and be active in improving our process. Management will also rely on you to assist in setting company directions and driving best practices vt being aware of developments in the field.
This position requires someone with a high energy level, strong communication skills and ability to work well as a part of a skilled development team.
• Constrained random functional verification and debug of digital and mixed signal designs
• To architect, create and modify a UVM/VMM/RVM based verification environments for chip level verification
• Technical leadership of digital verification efforts
• Behavioral modeling of complex analog functions and mixed level simulation of analog/digital circuits
• Supervising regressions and driving debug and functional coverage closure
• Prepare project plans and schedules
• Creation of technical documents (i.e. Verification Architecture Specifications)
• Work with analog engineers, system engineers and marketing to verification effort verifies customer and product requirements
• Provide leadership, guidance and mentoring to other Engineers
• Continual improvement of design quality and productivity.
• Review and enhance design methodology.
• A B.Sc. degree in Electrical or Computer Engineering and minimum 5+ years relevant industry experience with a preference for more than 7 years
• Expert knowledge and demonstrated experience in constrained random verification using UVM, OVM, AVM, or VMM methodologies
• Demonstrated experience in verification and RTL debugging
• Demonstrated experience with object oriented languages, SystemVerilog is preferred
• Demonstrated experience in creation of SystemVerilog assertions or similar
• Demonstrated experience with multiple simulation and debug tools (Mentor Modelsim; Synopsys VCS, Verdi; etc.)
• Familiarity with mixed signal simulation is preferred
• Familiarity with gate-level simulation is preferred
• Experience with related programming/scripting languages e.g. TCL, Perl, and C.
• Working knowledge of PC and Unix/Linux operating systems.
• Knowledge of digital design and verification methods and best practices
• Strong analytical and problem solving skills
• Excellent verbal and written communication skills
• Ability to work independently and in a team environment
• Ability to work with a multi-site team
• Excellent interpersonal and team skills
• Self-motivated and creative
• Well organized, thorough, and detail oriented
• Ability to multitask and prioritize multiple simultaneous responsibilities