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Futurewei Technology Baseband SoC group is looking for a world class Sr. Wireless Basestation L2/L3 and SoC/CPU System Architects to lead our effort to develop low power BTS Multi-Core Baseband SoC architecture for multimode (UMTS/LTE/GSM) platform. We are constantly looking for ways to improve the power efficiency, modularity, scalability, and reliability. In this technical leadership position, you will not only provide eye-popping beautiful pictures, more importantly develop reachable goals and concrete road map with your rich hands-on implementation experiences. You will be responsible for developing and enhancing various solutions in the multi-core BB SoC architecture that advance the state of the art in multimode operations, power efficiency, modularity, scalability, reliability and low cost of maintenance. You would interact with other world-class architects and researchers to design and validate these new features.
- Analyze market and live network data and predict wireless broadband evolution roadmap in terms traffic growth, traffic characteristics, user experience, operator requirements, etc
- Define the best competitive basestation SoC features and architecture in the industry, including performance, power efficiency, scalability.
- Derive use cases for multimode SoC that supports GSM/UMTS/LTE simultaneous multimode operation with different supporting levels for different markets
- Analyze in-house algorithms and develop data flow for the SoC architecture, with focus on L2 and L3, including
- Partitioning of function blocks, describing how these blocks work together,
- Analyzing their timing relationship, traffic between these bocks, and latency requirements, etc.
- Analyze benchmark and system requirements to derive CPU core/cluster architecture features and SoC architecture features.
- Search for optimization via CPU architecture modeling/profiling analysis for wireless application use cases to achieve best area/power/performance-gain trade off
- Work closely with SoC HW architecture design team to define requirements and specifications for CPU cluster architecture features and SoC architecture features, together with:
- computation complexity requirement analysis, computation characteristics analysis
- traffic analysis, latency analysis
- memory hierarchy requirement analysis, DDR requirement analysis
- multi-mode isolation/protection/virtualization
- debug and trace requirements
- Closely work with compiler team to search for joint optimization
- Build benchmarks for CPU cluster design and propose performance evaluation criteria and performance validation approaches supporting different stages of the system design
- Support ESL team to build the SoC system level simulation and identify the bottlenecks in the system and propose improvements
- Propose algorithm and SW joint optimization to reduce complexity with acceptable performance compromise.
- Conduct in-depth competition analysis; propose system requirement roadmap and SoC development roadmap for the L1/L2/L3 design.
- Minimum requirement, MS with 5 years related job responsibilities
- In-depth understanding of LTE/LTE-A, UMTS/HSPA+ specification, excellent understanding of L2/L3 procedure and good understanding of L1 signal processing algorithms; where LTE knowledge and skill is a must.
- Hands on experience in system requirement analysis to support multi-core SoC architecture design
- Good understanding of real time operating system, SW architecture, especially for LTE L2/L3 SW.
- In-depth understanding of memory hierarchy, cache coherence, interconnect and DDR controller.
- Hands on experience in multicore SoC and CPU cluster architecture features and performance evaluation, and area/power/performance tradeoff
- Hands on experience in CPU architecture/micro-architecture modeling/profiling analysis, code and trace quantitative analysis.
1. Excellent analytic skill
2. Excellent verbal and written communication skills
3. Excellent skill to work well in a multi team environment