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Sr. Wireless Basestation L2/L3 SoC/CPU System Architect

Location: Santa Clara, CA
Req #: 5203
# of Openings: 1

The Opportunity:

As a company, we are committed to creating maximum value for telecom operators, enterprises and consumers by providing competitive solutions and services. Our products and solutions have been deployed in over 140 countries, serving more than one third of the world’s population. Huawei's vision is to enrich life through communication.



Futurewei Technology Baseband SoC group is looking for a world class Sr. Wireless Basestation L2/L3 and SoC/CPU System Architects to lead our effort to develop low power BTS Multi-Core Baseband SoC architecture for multimode (UMTS/LTE/GSM) platform. We are constantly looking for ways to improve the power efficiency, modularity, scalability, and reliability. In this technical leadership position, you will not only provide eye-popping beautiful pictures, more importantly develop reachable goals and concrete road map with your rich hands-on implementation experiences. You will be responsible for developing and enhancing various solutions in the multi-core BB SoC architecture that advance the state of the art in multimode operations, power efficiency, modularity, scalability, reliability and low cost of maintenance. You would interact with other world-class architects and researchers to design and validate these new features.


  1. Analyze market and live network data and predict wireless broadband evolution roadmap in terms traffic growth, traffic characteristics, user experience, operator requirements, etc
  2. Define the best competitive basestation SoC features and architecture in the industry, including performance, power efficiency, scalability.
  3. Derive use cases for multimode SoC that supports GSM/UMTS/LTE simultaneous multimode operation with different supporting levels for different markets
  4. Analyze in-house algorithms and develop data flow for the SoC architecture, with focus on L2 and L3, including
    1. Partitioning of function blocks, describing how these blocks work together,
    2. Analyzing their timing relationship, traffic between these bocks, and latency requirements, etc.
  5. Analyze benchmark and system requirements to derive CPU core/cluster architecture features and SoC architecture features.
  6. Search for optimization via CPU architecture modeling/profiling analysis for wireless application use cases to achieve best area/power/performance-gain trade off
  7. Work closely with SoC HW architecture design team to define requirements and specifications for CPU cluster architecture features and SoC architecture features, together with:
    1. computation complexity requirement analysis, computation characteristics analysis
    2. traffic analysis, latency analysis
    3. memory hierarchy requirement analysis, DDR requirement analysis
    4. multi-mode isolation/protection/virtualization
    5. debug and trace requirements
  8. Closely work with compiler team to search for joint optimization
  9. Build benchmarks for CPU cluster design and propose performance evaluation criteria and performance validation approaches supporting different stages of the system design   
  10. Support ESL team to build the SoC system level simulation and identify the bottlenecks in the system and propose improvements
  11. Propose algorithm and SW joint optimization to reduce complexity with acceptable performance compromise.  
  12. Conduct in-depth competition analysis; propose system requirement roadmap and SoC development roadmap for the L1/L2/L3 design.



  1. Minimum requirement, MS with 5 years related job responsibilities  
  2. In-depth understanding of LTE/LTE-A, UMTS/HSPA+ specification, excellent understanding of L2/L3 procedure and good understanding of L1 signal processing algorithms; where LTE knowledge and skill is a must.
  3. Hands on experience in system requirement analysis to support multi-core SoC architecture design
  4. Good understanding of real time operating system, SW architecture, especially for LTE L2/L3 SW.
  5. In-depth understanding of memory hierarchy, cache coherence, interconnect and DDR controller.
  6. Hands on experience in multicore SoC and CPU cluster architecture features and performance evaluation, and area/power/performance tradeoff
  7. Hands on experience in CPU architecture/micro-architecture modeling/profiling analysis, code and trace quantitative analysis.

Other Requirement

1. Excellent analytic skill

2. Excellent verbal and written communication skills

3. Excellent skill to work well in a multi team environment


Why work for us?

- We are the global No. 1 telecom solution provider serving 45 of the world's top 50 operators
- Recognized on World's Most Innovative Companies List - 3 consecutive years by Fast Company Magazine
- Unprecedented growth - Double digit % growth in revenues every year since 2006
- Our contract sales reached $32.4 billion USD in 2012, a year on year increase of 11+%
- We invest in engineering and innovation - 62,000+ of our 140,000 global employees work in R&D
- We filed 36,344 patent applications in 2011 – globally ranked #3 for International Patent Submissions
- We continually invest heavily in global community involvement programs
- We support green energy - Lowered CO2 emissions by 13,000 tons via Huawei’s green packaging solutions
- We are a member of 130 standard bodies
- We are a global leader providing LTE infrastructure and commercialization - ranked No. 1 worldwide with 50%+ market share (Nov-2011)


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